Engineering Plan :: essays research papers

Engineering PlanWe plan to implement the basic multi-cycle processor throw as shown in the textbook, as well as pipelining and jumping and impinging. The toughest part of this design pass on be the datapath control, for which we lead be using a FSM. The ALU will implement add, sub, and, or, sll, and slt functions though a let on block is typically go ford for shift operations, we felt that putting sll and srl in the ALU would simplify our design. All other basic functions (lw, sw, lui, beq, bne, j) will be implemented as show in the textbook.The processor will have dickens main stages load pedagogicss into memory and execute instructions. Special instruction codes will be defined as stall and stop capital punishment to work in conjunction with the FSM. The global re frame will set all memory and registers to 0, and put the FSM in load instructions regularity. We would like to use one memory module to store twain instructions and data (with instructions starting at 0 an d deprivation up, and memory starting at the highest address and going down), however this design would present some addressing headaches so we will most promising use separate memory modules for instructions and data.The main part of the pipelining implementation will be the hazard detection unit of measurement. We plan to have this work autarkic of the datapath control FSM as so to simplify FSM design. The hazard detection unit will control muxes to drive register forwarding and will smother stall instructions directly to the instruction register when needed.Jump and link will make use of a specially designated register (most likely one of the upper registers, since those arent used in the provided test function). Muxes will be used to feed the PC+4 into the regfile and the regfile output into the PC register. The datapath control FSM will control these muxes.